1. Field of Invention
The present invention generally relates to a semiconductor package, and more particularly, to a semiconductor package which has a novel shape featuring a light, thin, compact, and miniaturized structure.
2. Description of the Related Art
The technology industry has provided products that feature light weight, miniaturization, and multi-functionality. One way this has been provided has been through a semiconductor package that incorporates a driving chip and a memory chip constructed in one module. Furthermore, the driving chip and the memory chip are fabricated as separate packages, and are either vertically or horizontally mounted on a mother board.
FIGS. 1 and 2 are cross-sectional views illustrating conventional semiconductor packages. FIG. 1 is a cross-sectional view illustrating a structure in which a driving package 10 and a memory package 20 are vertically stacked, and FIG. 2 is a cross-sectional view illustrating a structure in which a driving package 10 and a memory package 20 are horizontally mounted on a mother board 30.
However, when the driving package 10 and the memory package 20 are vertically stacked, a signal transfer path between the driving package 10 and the memory package 20 grows physically and in complexity which may cause problems, and when the driving package 10 and the memory package 20 are horizontally mounted on the mother board 30, the occupancy area of the mother board 30 increases, thereby adding difficulty to meet miniaturization demands.
Within the memory package 20, in order to realize a product that features a memory capacity capable of holding twice as much information compared to that of a single-chip memory, at least two memory chips 2 are stacked and connected with a substrate 3 via wires W. Subsequently, in order to protect the memory package 20, a molding part 5 is formed to seal the upper surface of the substrate 3 and the stacked memory chips 2.
Since wires W may have loops for preventing short-circuiting with peripheral components of the memory chips 2, the size of the memory package 20 increases due to the presence of the wire loops, which goes against the efforts of miniaturization. Also, a spacer 4 may be additionally formed between the stacked memory chips 2 to secure the height of the wire loops. As the number of stacked memory chips 2 increases, the height of the wire loops which are formed on the upper surface of the memory chip accordingly increases, thereby causing limitations in the number of memory chips 2 to be stacked. Moreover, as the number of stacked memory chips 2 increases, the length of wires W accordingly increases, which may cause problems such as wire sweeping, wire damage, and short-circuiting between peripheral components of the memory chips 2 and the wires W during a process for forming the molding part 5. In addition, since the wires W may be formed using gold, the package fabrication cost may substantially increase. In a memory chip such as a DRAM, which is fabricated to have a center pad structure, redistribution lines may be additionally formed to redistribute bonding pads to an edge of a chip for wire bonding, adding further complexity to the process. When grinding the memory chips 2 as thin as possible, although the number of memory chips 2 to be stacked may increase, failures such as warpage and cracking is likely to occur.